What does a PCB designer do
Allegro PCB Designer
Net scheduling or determining the order in which a network is contacted is useful for defining network topologies. A network with several connected components is divided internally into point-to-point connections in a defined sequence. Design rules can then also be assigned to the subnets. With a Daisy Chain or FlyBy topology, a sequence 1, 2, 3, 4, ... is defined. This is used e.g. with DDR3. When a DDR2 memory structure is defined, there are also branches where there are also rules that describe that branches of a network must be of the same length. But it can also be useful for low-speed circuits such as a power supply. A current of 20 amps flows from 1 to 2, from 2 to 3 only three amps and from 3 to 4 the voltage drop is measured via a sense control line. According to the Netscheduling, the conductor track widths can also be defined as a design rule according to the maximum current strength.
Dynamic Design For Assembly (DFA)
When assembling components on printed circuit boards, there are different minimum distances that are specified by the automatic assembly machine. You can define these minimum distances in the Constraint Manager. There are different values in the definition, depending on the type of component (e.g. SMD, BGA, ...) and the spatial arrangement in which the components are assembled next to each other. During placement, the minimum distance is displayed as a circle and at the same time the component at the cursor snaps onto this value. In this way, components can be placed extremely densely and all placement specifications of the assembler can be adhered to.
Interconnect Flow Designer (IFD)
When designs are complex, it is no longer possible to achieve optimal component placement right away. The solution is to plan a routing beforehand. The Interconnect Flow Planner function supports this. Networks can be defined in bundles and thus combined into logical units. A bundle shows the minimum width for routing, as it adds up the track width and the required track spacing of all signals in the bundle and displays them as a wide line. Bundles can be laid very easily on the circuit board. This intermediate level of auxiliary lines (bundles) enables the connection of signals with their space requirements to be displayed during routing. With this technique, routing can be planned in advance, in that the layouter already distributes the signals to layers. With this information from the bundles, the placement of components and routing channels can be carried out at the same time and ultimately the space requirements of a circuit board can be optimized. Bundles describe the design intent and can also be shown or hidden after or during routing. Bundles remain in the database and the design intent is also available for later redesigns.
ECAD-MCAD (.idx file)
Miniaturization usually requires an optimized integration of printed circuit boards in mechanical housings. The previous formats (DXF and IDF) for exchanging eCAD and mCAD data have limitations. That is why the ProStep consortium, consisting of many EDA and mCAD manufacturers and users from various industries, has agreed on the definition of a new EDMD (.ifx) standard. The Allegro PCB Designer supports this new format for incremental and documented data exchange.
Back three of a kind
If signals with high frequencies are transmitted in a PCB, then unconnected cable stubs are like antennas and cause SI and EMC problems. This occurs, for example, when a signal on a through-hole (via 1-8) only changes from position 2 to position 3. Then from 3-8 an unused piece of via remains in the circuit board. With the backdrill function, rule-compliant and optimized manufacturing instructions are generated where and how deep this residual piece is removed with a drill. Backdrilling is typically used from clock rates of 3GBit / s.
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