What is the propagation delay in digital circuits

Design Considerations for Digital VLSI

Design Considerations for Digital VLSI

Design procedures in VLSI SoCs are very complex. The designer should consider all possible states and inputs and design the chip to work every time in every state and with every possible input. In this article we discuss metastability, setup time, and hold time when designing a digital VLSI circuit.

Critical path, throughput, and latency

The critical path is the longest path in the circuit and limits the clock speed. There are two other important factors to consider when describing a digital circuit: latency and throughput. Latency is the time it takes for an input change to produce an output change; Latency can be expressed as a length of time or, in synchronous circuits, as a certain number of clock cycles. Throughput refers to the rate at which data can be processed.

Flip-flops and combinational logic

A digital circuit can consist of sequential logic and combinational logic. Sequential logic refers to circuits whose output depends on previous states. In other words, it is a memory that stores previous states and enables a decision based on these previous states and the current input signals. In the digital realm, flip-flops are the standard devices used to store previous logic states. In Verilog we can define a flip-flop using the reg command:

reg (7: 0) states;

The line above defines an 8-bit flip-flop. Sensitive to clock transitions rather than clock logic states, flip-flops are the most basic element of synchronous designs.

Combinational logic refers to a circuit that calculates an output based only on the current input signals.

Illustration 1. sh = ab '+ bc. Image courtesy of Tampere University of Technology

A simple combinational logic circuit is implemented in FIG. Each logic device has a propagation delay. The transit time delay is the time difference between an input change and the corresponding output change. This delay can lead to unexpected behavior, such as when a gate accepts two inputs that come from paths with a different number of gates (and therefore have an unequal total propagation delay).

Suppose we are in the (1, 1, 1) input state and the output is stable at 1. When b changes from 1 to zero, the output of the lower AND gate will pass before that of the upper AND gate, resulting in a temporary result logic low on the output. This logic low state is invalid because a (1, 0, 1) input pattern should produce a logic high output. This brief, invalid initial state is known as danger.

More precisely, this disturbance is known as static hazard. Dynamic hazards occur when an input change results in more than one output error. As a rule, dynamic hazards occur in complex circuits with several gates and logical paths.

In the synchronous design, we have to ensure that interference does not lead to invalid output states. As mentioned above, designers commonly use edge-sensitive flip-flops to store past states. When using flip-flops in digital VLSI designs we need to keep the following in mind:

  1. Setup time: the input to a flip-flop should be stable for a certain amount of time (the setup time) before the clock transitions; otherwise the flip-flop will behave in an unstable manner, which is known as metastability.
  2. Hold time: The input of a flip-flop should remain stable for a certain time (the hold time) after the clock has passed.

The following illustration provides a visual description of the setup time and hold time:

Figure 2. Setup and hold time definitions. Image courtesy of Tampere University of Technology

Construction time

A digital circuit designed for FPGA or ASIC purposes requires combinational logic for calculations. We usually build multipliers, subtractors, adders, etc. with logic gates. We use flip-flops to store input and output values ​​for these combinational logic circuits. Flip-flops are at the beginning and end of all critical paths as shown in Figure 3.

In order to avoid violating the setup time when using flip-flops at the end of a combinatorial path, the output must be stable before the clock edge. Thus, the total propagation delay of a combinational path must not cause the output to skip so that the relationship between the clock signal and the data signal leads to a setup time violation.

Figure 3. An example of a synchronous digital circuit.


In VLSI designs, we can face a very long critical path due to an extensive combinatorial circuit. In such cases, the clock speed is slowed to ensure that the delays associated with the critical path do not result in setup time violations. Pipelining is a technique where we break a combinatorial path into several parts and include a register at the end of each subpath. In this way we split the critical path into several small paths and this allows us to increase the clock speed and, consequently, the throughput of the circuit.

For example, in Figure 4 we have a long critical path that limits the clock frequency. However, the split and pipelined path (see Figure 5) contains shorter combinatorial paths and that means we can increase the clock speed. In return, however, the latency of the path increases.

Figure 4. Long combinatorial logic path. Image courtesy of Sharif University of Technology (PDF)
Figure 5. Pipelining the circuit of Figure 4. Image courtesy of Sharif University of Technology (PDF)

Hold time

The input to a flip-flop should be stable for a period equal to or greater than the hold time. For example, in FIG. 6, it is assumed that the combinational path delay between FF1 and FF2 is 0.7 ns, the flip-flop setup time is 2 ns, and its hold time is 1 ns. If we assume that the propagation delay of the flip-flops is zero, the output of FF1 will change immediately after a clock edge, and after 0.7 seconds the signal has passed through the combinational logic and has arrived at the FF2 input. However, the input to FF2 should be stable for at least 1 ns after the clock edge. Therefore, a hold time violation occurs.

Figure 6. Example of a time violation violation Image courtesy of the VLSI Expert Group

A setup time violation can be resolved by reducing the clock frequency even after the device has been manufactured; However, a hold time violation cannot be corrected if it is discovered after the manufacturing process. The most important thing is to design our circuit in such a way that there are no hold time violations. a combinatorial circuit connected to a flip-flop input should have a propagation delay compatible with the hold time requirement.

One technique for avoiding hold time violations is to increase the delay of a fast path by adding buffers. Today, CAD tools can help identify parts of a design that may have hold or setup time violations. In addition, CAD tools can take into account the timing requirements of synthesizing, placing, and routing a particular design.

Clock crossing

Most modern designs use multiple clock frequencies. ADCs or DACs may have a clock that is not synchronized with the FPGA clock, and yet the ADC or DAC signals must be introduced into the FPGA clock domain. When working with multiple clock domains, we need to be careful to avoid situations that could lead to metastability.

We have to achieve synchronization between different clock domains. This can be done by using a simple FIFO that has a clock for input and a separate clock for output. We could also use a basic shift register instead of a FIFO. The following Verilog code can be used to provide synchronization between different clock domains.

We can also use asynchronous design techniques to address problems associated with multiple clock domains, but we'll look at that in a future article. We'll also wait until the next article to cover more important topics like the following:

  • Clock skew and handling of clock skew using clock distribution trees
  • Problems related to the use of gated clocks in FPGAs
  • Flip-flops with negative hold time


In this article, we've talked about hold time violations and how to avoid them by adding a delay to fast logic paths. We have also explained setup time violations and we have discussed pipelining as a method of avoiding timing problems in circuits that involve a long critical path. Finally, we introduced the idea of ​​multiple clock domains and looked at a simple Verilog approach to clock synchronization.